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| - 1 - m393t2863fba m393t5663fba rev. 1.0, jul. 2010 samsung electronics reserves the right to change products, information and specifications without notice. products and specifications discussed herein are for reference pur poses only. all info rmation discussed herein is provided on an "as is" bas is, without warranties of any kind. this document and all information discussed herein re main the sole and exclusive property of samsung electronics. no license of any patent, copyright, mask work, tradem ark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other- wise. samsung products are not intended for use in life sup port, critical care, medical, safety equipment, or similar applications where pr oduct failure could result in loss of li fe or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. for updates or additional information about samsung products, contact your nearest samsung office. all brand names, trademarks and registered tradem arks belong to their respective owners. ? 2010 samsung electronics co., ltd. all rights reserved. m393t5660fba datasheet m393t5160fba 240pin registered dimm based on 1gb f-die 60 fbga with lead-free & halogen-free (rohs compliant)
- 2 - datasheet ddr2 sdram rev. 1.0 registered dimm revision history revision no. history draft date remark editor 1.0 - first release jul. 2010 - s.h.kim - 3 - datasheet ddr2 sdram rev. 1.0 registered dimm table of contents 240pin registered dimm based on 1gb f-die 1. ddr2 unbuffered dimm ordering info rmation ........ .............. .............. .............. ........... ........... ........... .......................... 4 2. key features................................................................................................................ ................................................. 4 3. address configuration ....................................................................................................... ........................................... 4 4. pin configurations (front side/back side)....... ............................................................................ .................................. 5 5. pin description ............................................................................................................. ................................................. 5 6. input/output function description ..................... ...................................................................... ..................................... 6 7. functional block diagram : .................................................................................................. ......................................... 7 7.1 1gb, 128mx72 module - m393t2863f ba ................. .............. .............. ........... ........... ............ .......... ..................... 7 7.2 2gb, 256mx72 module - m393t5663f ba ................. .............. .............. ........... ........... ............ .......... ..................... 8 7.3 2gb, 256mx72 module - m393t5660f ba ................. .............. .............. ........... ........... ............ .......... ..................... 9 7.4 4gb, 512mx72 module - m393t5160f ba ................. .............. .............. ........... ........... ............ .......... ..................... 10 8. absolute maximum dc ratings ... .............................................................................................. ................................... 11 9. ac & dc operating conditions................................................................................................ ..................................... 11 9.1 recommended dc operating conditions (sstl - 1.8).... ....................................................................... ................ 11 9.2 operating temperature condition ............................................................................................ ............................... 12 9.3 input dc logic level ....................................................................................................... ........................................ 12 9.4 input ac logic level ....................................................................................................... ........................................ 12 9.5 ac input test conditions................................................................................................... ...................................... 12 10. idd specification parameters definition ............. ....................................................................... ................................. 13 11. operating current table : .................................................................................................. ......................................... 14 11.1 m393t2863fba : 1gb(128mx8 *9) module................ .............. .............. .............. .............. .............. .................... 14 11.2 m393t2863fba : 1gb(128mx8 *9) module - considering regi ster and pll current value .............. ........... ......... 14 11.3 m393t5663fba : 2gb(128mx8 *18) module ........... .............. .............. .............. ........... ........... .......... ................... 15 11.4 m393t5663fba : 2gb(128mx8 *18) module - considering register and pll current va lue......... .............. ......... 15 11.5 m393t5660fba : 2gb(256mx4 *18) module ........... .............. .............. .............. ........... ........... .......... ................... 16 11.6 m393t5660fba : 2gb(256mx4 *18) module - considering register and pll current va lue......... .............. ......... 16 11.7 m393t5160fba : 4gb(256mx4 *36) module ........... .............. .............. .............. ........... ........... .......... ................... 17 11.8 m393t5160fba : 4gb(256mx4 *36) module - considering register and pll current va lue......... .............. ......... 17 12. input/output capacitance ................................................................................................... ........................................ 18 13. electrical characteristics & ac timing for ddr2-800/ 667 ............. .............. .............. .............. ............. ..................... 18 13.1 refresh parameters by device density...................................................................................... ........................... 18 13.2 speed bins and cl, trcd, trp, trc and tras for corre sponding bin ....... .............. .............. ............ ........... ...... 18 13.3 timing parameters by speed grade ......................................................................................... ........................... 19 14. physical dimensions : ................................... ................................................................... ........................................... 21 14.1 128mbx8 based 128mx72 module (1 rank)............. ........................................................................ ..................... 21 14.2 128mbx8/256mbx4 based 256m x72 module (2 ranks / 1 rank)............... .............. .............. .............. .......... ....... 22 14.3 256mbx4 based 512mx72 module (2 ranks) ........... ......................................................................... .................... 23 15. 240 pin ddr2 registered dimm clock topology ......... ....................................................................... ...................... 24 - 4 - datasheet ddr2 sdram rev. 1.0 registered dimm 1. ddr2 unbuffered dimm ordering information note : 1. ?b? of part number(11th digit) stands for lead-free, halogen-free, and rohs compliant products. 2. ?a? of part number(12th digit) stands for parity register products. 2. key features ? performance range e7 (ddr2-800) f7 (ddr2-800) e6 (ddr2-667) unit ? jedec standard v dd = 1.8v 0.1v power supply ?v ddq = 1.8v 0.1v ? 267mhz f ck for 533mb/sec/pin, 333mhz f ck for 667mb/sec/pin, 400mhz f ck for 800mb/sec/pin ? 8 banks ? posted cas ? programmable cas latency: 3, 4, 5, 6 ? programmable additive latency: 0, 1 , 2 , 3, 4, 5 ? write latency(wl) = read latency(rl) -1 ? burst length: 4 , 8(interleave/nibble sequential) ? programmable sequential / interleave burst mode ? bi-directional differential data-strobe (s ingle-ended data-strobe is an optional feature) ? off-chip driver(ocd) impedance adjustment ? on die termination with selectabl e values(50/75 /150 ohms or disable) ? average refresh period 7.8us at lower than a t case 85 c, 3.9us at 85 c < t case < 95 c - support high temperature self-refresh rate enable feature ? serial presence detect with eeprom ? ddr2 sdram package: 60ball fbga(flip-chip) - 256mx4/128mx8 ? all of products are lead-free, halogen-free, and rohs compliant note : for detailed ddr2 sdram operation, please refer to samsung?s device operation & timing diagram. 3. address configuration part number density organization component composition number of rank height M393T2863FBA-CE7/f7/e6 1gb 128mx72 128mx8(k4t1g084qf)*9 1 30mm m393t5663fba-ce7/f7/e6 2gb 256mx72 128mx8(k4t1g084qf)*18 2 30mm m393t5660fba-ce7/f7/e6 2gb 256mx72 256mx4(k4t1g084qf)*18 1 30mm m393t5160fba-ce7/f7/e6 4gb 512mx72 256mx4(k4t1g084qf)*36 2 30mm cas latency 5 65 tck trcd(min) 12.5 15 15 ns trp(min) 12.5 15 15 ns trc(min) 57.5 60 60 ns organization row address column address bank address auto precharge 256mx4(1gb) based module a0-a13 a0-a9, a11 ba0-ba2 a10 128mx8(1gb) based module a0-a13 a0-a9 ba0-ba2 a10 - 5 - datasheet ddr2 sdram rev. 1.0 registered dimm 4. pin configurations (front side/back side) note : nc = no connect, rfu = reserved for future use 1. reset (pin 18) is connected to both oe of pll and reset of register. 2. the test pin (pin 102) is reserved for bus analysis pr obes and is not connected on normal memory modules (dimms) 3. nc/err_out ( pin 55) and nc/par_in (pin 68) are for optional function to check address and command parity. 5. pin description * the v dd and v ddq pins are tied to the single power-plane on pcb. pin front pin back pin front pin back pin front pin back pin front pin back 1v ref 121 v ss 31 dq19 151 v ss 61 a4 181 v ddq 91 v ss 211 dm5/dqs14 2v ss 122 dq4 32 v ss 152 dq28 62 v ddq 182 a3 92 dqs 5 212 nc/dqs 14 3 dq0 123 dq5 33 dq24 153 dq29 63 a2 183 a1 93 dqs5 213 v ss 4 dq1 124 v ss 34 dq25 154 v ss 64 v dd 184 v dd 94 v ss 214 dq46 5v ss 125 dm0/dqs9 35 v ss 155 dm3/dqs12 key 95 dq42 215 dq47 6dqs 0 126 nc/dqs 936 dqs 3 156 nc/dqs 12 65 v ss 185 ck0 96 dq43 216 v ss 7 dqs0 127 v ss 37 dqs3 157 v ss 66 v ss 186 ck 097 v ss 217 dq52 8v ss 128 dq6 38 v ss 158 dq30 67 v dd 187 v dd 98 dq48 218 dq53 9 dq2 129 dq7 39 dq26 159 dq31 68 nc/par_in 188 a0 99 dq49 219 v ss 10 dq3 130 v ss 40 dq27 160 v ss 69 v dd 189 v dd 100 v ss 220 s 2 11 v ss 131 dq12 41 v ss 161 cb4 70 a10/ap 190 ba1 101 sa2 221 s 3 12 dq8 132 dq13 42 cb0 162 cb5 71 ba0 191 v ddq 102 nc(test) 222 v ss 13 dq9 133 v ss 43 cb1 163 v ss 72 v ddq 192 ras 103 v ss 223 dm6/dqs15 14 v ss 134 dm1/dqs10 44 v ss 164 dm8/dqs17 73 we 193 s 0104dqs 6 224 nc/dqs 15 15 dqs 1 135 nc/dqs 10 45 dqs 8 165 nc/dqs 17 74 cas 194 v ddq 105dqs6225 v ss 16 dqs1 136 v ss 46 dqs8 166 v ss 75 v ddq 195 odt0 106 v ss 226 dq54 17 v ss 137 rfu 47 v ss 167 cb6 76 s 1 196 a13 107 dq50 227 dq55 18 reset 138 rfu 48 cb2 168 cb7 77 odt1 197 v dd 108 dq51 228 v ss 19 nc 139 v ss 49 cb3 169 v ss 78 v ddq 198 v ss 109 v ss 229 dq60 20 v ss 140 dq14 50 v ss 170 v ddq 79 v ss 199 dq36 110 dq56 230 dq61 21 dq10 141 dq15 51 v ddq 171 cke1 80 dq32 200 dq37 111 dq57 231 v ss 22 dq11 142 v ss 52 cke0 172 v dd 81 dq33 201 v ss 112 v ss 232 dm7/dqs16 23 v ss 143 dq20 53 v dd 173 nc 82 v ss 202 dm4/dqs13 113 dqs 7 233 nc/dqs 16 24 dq16 144 dq21 54 ba2 174 nc 83 dqs 4 203 nc/dqs 13 114 dqs7 234 v ss 25 dq17 145 v ss 55 nc/err_out 175 v ddq 84 dqs4 204 v ss 115 v ss 235 dq62 26 v ss 146 dm2/dqs11 56 v ddq 176 a12 85 v ss 205 dq38 116 dq58 236 dq63 27 dqs 2 147 nc/dqs 11 57 a11 177 a9 86 dq34 206 dq39 117 dq59 237 v ss 28 dqs2 148 v ss 58 a7 178 v dd 87 dq35 207 v ss 118 v ss 238 v ddspd 29 v ss 149 dq22 59 v dd 179 a8 88 v ss 208 dq44 119 sda 239 sa0 30 dq18 150 dq23 60 a5 180 a6 89 dq40 209 dq45 120 scl 240 sa1 90 dq41 210 v ss pin name description pin name description ck0 clock inputs, positive line odt0~odt1 on die termination ck 0 clock inputs, negative line dq0~dq63 data input/output cke0, cke1 clock enables cb0~cb7 data check bits input/output ras row address strobe dqs0~dqs8 data strobes cas column address strobe dqs 0~dqs 8 data strobes, negative line we write enable dm(0~8),dqs(9~17) data masks / data strobes (read) s 0~ s 3chip selects dqs 9~dqs 17 data strobes (read), negative line a0~a9, a11~a13 address inputs rfu reserved for future use a10/ap address input/autoprecharge nc no connect ba0~ba2 ddr2 sdram bank address test memory bus test tool (not connect and not useable on dimms) scl serial presence detect (spd) clock input v dd core power sda spd data input/output v ddq i/o power sa0~sa2 spd address v ss ground par_in parity bit for the address and control bus v ref input/output reference err_out parity error found in the address and control bus v ddspd spd power reset register and pll control pin - 6 - datasheet ddr2 sdram rev. 1.0 registered dimm 6. input/output function description ck0 input positive line of the differential pair of system clock inputs that dr ives input to the on-dimm pll. ck 0 input negative line of the differential pai r of system clock inputs that dr ives the input to the on-dimm pll. cke0~cke1 input activates the sdram ck signal when hi g h and deactivates the ck signal when low. by deactivating th e clocks, cke low initiates the power down mode, or the self refresh mode. 0~ 3 input enables the associated sdram command decoder when low and disables decoder when hi gh. when decoder is dis - abled, new commands are ignored bu t previo us operations continue. these input signals also disable all outputs (except cke and odt) of the register(s) on the dimm when both inputs are high. odt0~odt1 input i/o bus impedance control signals. r as , we input when sampled at the positive rising edge of the clock, , , and define the operation to be executed by the sdram. v ref supply reference voltage for sstl_18 inputs v ddq supply isolated power supply for the ddr sdram output buff ers to provide im proved noise immunity ba0~ba2 input selects which sdram bank of eight is activated. a0~a9,a10/ap a11~a13 input during a bank activate command cycl e, addr ess defines the row address. symbol type description s s cas , cas ras we - 7 - datasheet ddr2 sdram rev. 1.0 registered dimm 7. functional block diagram : 7.1 1gb, 128mx72 module - m393t2863fba (populated as 1 rank of x8 ddr2 sdrams) rs 0 dqs0 dqs 0 dm0/dqs9 nc/dqs 9 dm/ rdqs nu/ rdqs cs dqs dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d0 dqs1 dqs 1 dm1/dqs10 nc/dqs 10 dm/ rdqs nu/ rdqs cs dqs dqs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d1 dqs2 dqs 2 dm2/dqs11 nc/dqs 11 dm/ rdqs nu/ rdqs cs dqs dqs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d2 dqs3 dqs 3 dm3/dqs12 nc/dqs 12 dm/ rdqs nu/ rdqs cs dqs dqs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d3 dqs8 dqs 8 dm8/dqs17 nc/dqs 17 dm/ rdqs nu/ rdqs cs dqs dqs cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d8 dqs4 dqs 4 dm4/dqs13 nc/dqs 13 dm/ rdqs nu/ rdqs cs dqs dqs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d4 dqs5 dqs 5 dm5/dqs14 nc/dqs 14 dm/ rdqs nu/ rdqs cs dqs dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d5 dqs6 dqs 6 dm6/dqs15 nc/dqs 15 dm/ rdqs nu/ rdqs cs dqs dqs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d6 dqs7 dqs 7 dm7/dqs16 nc/dqs 16 dm/ rdqs nu/ rdqs cs dqs dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d7 a0 serial pd a1 a2 sa0 sa1 sa2 scl sda v ss d0 - d8 v dd /v ddq d0 - d8 d0 - d8 v ref v ddspd serial pd wp note : 1. dq-to-i/o wiring may be changed within a byte. 2. dq/dqs/dm/cke/s relationships must be maintained as shown. 3. unless otherwise noted, resister values are 22 ohms r 5% 1:1 r e g i s t e r rst s0 * ba0-ba2 a0-a13 ras cas we cke0 odt0 reset pck7 pck 7 rs o-> cs : ddr2 sdrams d0-d8 rba0-rba2 -> ba0-ba2 : ddr2 sdrams d0-d8 ra0-ra13 -> a0-a13 : ddr2 sdrams d0-d8 rras -> ras : ddr2 sdrams d0-d8 rcas -> cas : ddr2 sdrams d0-d8 rwe -> we : ddr2 sdrams d0-d8 rcke0 -> cke : ddr2 sdrams d0-d8 rodt0 -> odt0 : ddr2 sdrams d0-d8 p l l oe ck 0 ck0 reset pck0-pck6, pck8, pck9 -> ck : ddr2 sdrams d0-d8 pck 0-pck 6, pck 8, pck 9 -> ck : ddr2 sdrams d0-d8 pck7 -> ck : register pck 7 -> ck : register * s 0 connects to dcs and v dd connects to csr on the register. s 1, cke1 and odt are nc. signals for address and command parity function v ss v ss par_in c0 c1 ppo qerr err_out register par_in 100k ohms the resistors on par_in, a14, a15, and the signal line of err_out refer to the section: "register options for unused address inputs" - 8 - datasheet ddr2 sdram rev. 1.0 registered dimm 7.2 2gb, 256mx72 module - m393t5663fba (populated as 2 ranks of x8 ddr2 sdrams) rs 0 dqs0 dqs 0 dm0/dqs9 nc/dqs 9 dm/ rdqs nu/ rdqs cs dqs dqs dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d0 dqs1 dqs 1 dm1/dqs10 nc/dqs 10 dm/ rdqs nu/ rdqs cs dqs dqs dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d1 dqs2 dqs 2 dm2/dqs11 nc/dqs 11 dm/ rdqs nu/ rdqs cs dqs dqs dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d2 dqs3 dqs 3 dm3/dqs12 nc/dqs 12 dm/ rdqs nu/ rdqs cs dqs dqs dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d3 dqs8 dqs 8 dm8/dqs17 nc/dqs 17 dm/ rdqs nu/ rdqs cs dqs dqs cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d8 dqs4 dqs 4 dm4/dqs13 nc/dqs 13 dm/ rdqs nu/ rdqs cs dqs dqs dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d4 dqs5 dqs 5 dm5/dqs14 nc/dqs 14 dm/ rdqs nu/ rdqs cs dqs dqs dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d5 dqs6 dqs 6 dm6/dqs15 nc/dqs 15 dm/ rdqs nu/ rdqs cs dqs dqs dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d6 dqs7 dqs 7 dm7/dqs16 nc/dqs 16 dm/ rdqs nu/ rdqs cs dqs dqs dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d7 dm/ rdqs nu/ rdqs cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d9 dm/ rdqs nu/ rdqs cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d10 dm/ rdqs nu/ rdqs cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d11 dm/ rdqs nu/ rdqs cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d12 dm/ rdqs nu/ rdqs cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d17 dm/ rdqs nu/ rdqs cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d13 dm/ rdqs nu/ rdqs cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d14 dm/ rdqs nu/ rdqs cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d15 dm/ rdqs nu/ rdqs cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 d16 rs 1 a0 serial pd a1 a2 sa0 sa1 sa2 scl sda v ss d0 - d17 v dd /v ddq d0 - d17 d0 - d17 v ref v ddspd serial pd wp note : 1. dq-to-i/o wiring may be changed per nibble. 2. unless otherwise noted, resister values are 22 ohms r 5% 3. rs 0 and rs 1 alternate between the back and front sides of the dimm 1:2 r e g i s t e r rst s1 * ba0-ba2 a0-a13 ras cas we cke0 cke1 reset ** pck7** pck 7** rs 1-> cs : ddr2 sdrams d9-d17 rba0-rba2 -> ba0-ba2: ddr2 sdrams d0-d17 ra0-ra13 -> a0-a13 : ddr2 sdrams d0-d17 rras -> ras : ddr2 sdrams d0-d17 rcas -> cas : ddr2 sdrams d0-d17 rwe -> we : ddr2 sdrams d0-d17 rcke0 -> cke : ddr2 sdrams d0-d8 rcke1 -> cke : ddr2 sdrams d9-d17 p l l oe ck 0 ck0 reset pck0-pck6, pck8, pck9 -> ck : ddr2 sdrams d0-d17 pck 0-pck 6, pck 8, pck 9 -> ck : ddr2 sdrams d0-d17 pck7 -> ck : register pck 7 -> ck : register odt0 odt1 rodt0 -> odt0 : ddr2 sdrams d0-d8 rodt1 -> odt1 : ddr2 sdrams d9-d17 s0 * rs o-> cs : ddr2 sdrams d0-d8 * s 0 connects to dcs and s 1 connects to csr on a register, s 1 connects to dcs and s 0 connects to csr on another register. ** reset , pck7 and pck 7 connects to both registers. other signals connect to one of two registers. signals for address and command parity function v ss v dd par_in c0 c1 ppo qerr register a par_in 100k ohms the resistors on par_in, a14, a15, and the signal line of err_out refer to the sec- tion: "register options for unused address inputs" v dd v dd c0 c1 ppo qerr err_out register b par_in - 9 - datasheet ddr2 sdram rev. 1.0 registered dimm 7.3 2gb, 256mx72 module - m393t5660fba (populated as 1 rank of x4 ddr2 sdrams) v ss rs 0 dqs0 dqs 0 dm cs dqs dqs dq0 dq1 dq2 dq3 i/o 0 i/o 1 i/o 2 i/o 3 d0 dm0/dqs9 nc/dqs 9 dm cs dqs dqs dq4 dq5 dq6 dq7 i/o 0 i/o 1 i/o 2 i/o 3 d9 dqs1 dqs 1 dm cs dqs dqs dq8 dq9 dq10 dq11 i/o 0 i/o 1 i/o 2 i/o 3 d1 dm1/dqs10 nc/dqs 10 dm cs dqs dqs dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 d10 dqs2 dqs 2 dm cs dqs dqs dq16 dq17 dq18 dq19 i/o 0 i/o 1 i/o 2 i/o 3 d2 dm2/dqs11 nc/dqs 11 dm cs dqs dqs dq20 dq21 dq22 dq23 i/o 0 i/o 1 i/o 2 i/o 3 d11 dqs3 dqs 3 dm cs dqs dqs dq24 dq25 dq26 dq27 i/o 0 i/o 1 i/o 2 i/o 3 d3 dm3/dqs12 nc/dqs 12 dm cs dqs dqs dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 d12 dqs5 dqs 5 dm cs dqs dqs dq40 dq41 dq42 dq43 i/o 0 i/o 1 i/o 2 i/o 3 d5 dm5/dqs14 nc/dqs 14 dm cs dqs dqs dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 d14 dqs4 dqs 4 dm cs dqs dqs dq32 dq33 dq34 dq35 i/o 0 i/o 1 i/o 2 i/o 3 d4 dm4/dqs13 nc/dqs 13 dm cs dqs dqs dq36 dq37 dq38 dq39 i/o 0 i/o 1 i/o 2 i/o 3 d13 dqs6 dqs 6 dm cs dqs dqs dq48 dq49 dq50 dq51 i/o 0 i/o 1 i/o 2 i/o 3 d6 dm6/dqs15 nc/dqs 15 dm cs dqs dqs dq52 dq53 dq54 dq55 i/o 0 i/o 1 i/o 2 i/o 3 d15 dqs8 dqs 8 dm cs dqs dqs cb0 cb1 cb2 cb3 i/o 0 i/o 1 i/o 2 i/o 3 d8 dm8/dqs17 nc/dqs 17 dm cs dqs dqs cb4 cb5 cb6 cb7 i/o 0 i/o 1 i/o 2 i/o 3 d17 dqs7 dqs 7 dm cs dqs dqs dq56 dq57 dq58 dq59 i/o 0 i/o 1 i/o 2 i/o 3 d7 dm7dqs16 nc/dqs 16 dm cs dqs dqs dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 d16 a0 serial pd a1 a2 sa0 sa1 sa2 scl sda v ss d0 - d17 v dd /v ddq d0 - d17 d0 - d17 v ref v ddspd serial pd wp note : 1. dq-to-i/o wiring may be changed per nibble. 2. unless otherwise noted, resister values are 22 ohms r 5% 1:2 r e g i s t e r rst s0 * ba0-ba2 a0-a13 ras cas we cke0 odt0 reset ** pck7** pck 7** rs o-> cs : ddr2 sdrams d0-d17 rba0-rba2 -> ba0-ba2 : ddr2 sdrams d0-d17 ra0-ra13 -> a0-a13 : ddr2 sdrams d0-d17 rras -> ras : ddr2 sdrams d0-d17 rcas -> cas : ddr2 sdrams d0-d17 rwe -> we : ddr2 sdrams d0-d17 rcke0 -> cke : ddr2 sdrams d0-d17 rodt0 -> odt0 : ddr2 sdrams d0-d17 p l l oe ck 0 ck0 reset pck0-pck6, pck8, pck9 -> ck : ddr2 sdrams d0-d8 pck 0-pck 6, pck 8, pck 9 -> ck : ddr2 sdrams d0-d8 pck7 -> ck : register pck 7 -> ck : register * s 0 connects to dcs of register1 and csr of register2. csr of register 1 and dcs of register 2 connects to v dd . ** reset , pck7 and pck 7 connects to both registers. other si gnals connect to one of two registers. s 1, cke1 and odt1 are nc. signals for address and command parity function v ss v dd par_in c0 c1 ppo qerr register a par_in 100k ohms the resistors on par_in, a14, a15, and the signal line of err_out refer to the section: "register options for unused address inputs" v dd v dd c0 c1 ppo qerr err_out register b par_in - 10 - datasheet ddr2 sdram rev. 1.0 registered dimm 7.4 4gb, 512mx72 module - m393t5160fba (populated as 2 ranks of x4 ddr2 sdrams) a0 serial pd a1 a2 sa0 sa1 sa2 scl sda v ss d0 - d35 v dd /v ddq d0 - d35 d0 - d35 v ref v ddspd serial pd wp p l l oe ck 0 ck0 reset pck0-pck6, pck8, pck9 -> ck : ddr2 sdrams d0-d35 pck 0-pck 6, pck 8, pck 9 -> ck : ddr2 sdrams d0-d35 pck7 -> ck : register pck 7 -> ck : register 1:2 r e g i s t e r rst s1 * ba0-ba1 a0-a13 ras cas we cke0 cke1 reset ** pck7** pck 7** rs 1-> cs : ddr2 sdrams d18-d35 rba0-rba1 -> ba0-ba1 : ddr2 sdrams d0-d35 ra0-ra13 -> a0-a13 : ddr2 sdrams d0-d35 rras -> ras : ddr2 sdrams d0-d35 rcas -> cas : ddr2 sdrams d0-d35 rwe -> we : ddr2 sdrams d0-d35 rcke0 -> cke : ddr2 sdrams d0-d17 rcke1 -> cke : ddr2 sdrams d18-d35 odt0 odt1 rodt0 -> odt0 : ddr2 sdrams d0-d17 rodt1 -> odt1 : ddr2 sdrams d18-d35 s0 * rs o-> cs : ddr2 sdrams d0-d17 v ss rs 0 dqs0 dqs 0 dm cs dqs dqs dq0 dq1 dq2 dq3 i/o 0 i/o 1 i/o 2 i/o 3 d0 dm0/dqs9 nc/dqs 9 dm cs dqs dqs dq4 dq5 dq6 dq7 i/o 0 i/o 1 i/o 2 i/o 3 d9 dqs1 dqs 1 dm cs dqs dqs dq8 dq9 dq10 dq11 i/o 0 i/o 1 i/o 2 i/o 3 d1 dm1/dqs10 nc/dqs 10 dm cs dqs dqs dq12 dq13 dq14 dq15 i/o 0 i/o 1 i/o 2 i/o 3 d10 dqs2 dqs 2 dm cs dqs dqs dq16 dq17 dq18 dq19 i/o 0 i/o 1 i/o 2 i/o 3 d2 dm2/dqs11 nc/dqs 11 dm cs dqs dqs dq20 dq21 dq22 dq23 i/o 0 i/o 1 i/o 2 i/o 3 d11 dqs3 dqs 3 dm cs dqs dqs dq24 dq25 dq26 dq27 i/o 0 i/o 1 i/o 2 i/o 3 d3 dm3/dqs12 nc/dqs 12 dm cs dqs dqs dq28 dq29 dq30 dq31 i/o 0 i/o 1 i/o 2 i/o 3 d12 dqs5 dqs 5 dm cs dqs dqs dq40 dq41 dq42 dq43 i/o 0 i/o 1 i/o 2 i/o 3 d5 dm5/dqs14 nc/dqs 14 dm cs dqs dqs dq44 dq45 dq46 dq47 i/o 0 i/o 1 i/o 2 i/o 3 d14 dqs4 dqs 4 dm cs dqs dqs dq32 dq33 dq34 dq35 i/o 0 i/o 1 i/o 2 i/o 3 d4 dm4/dqs13 nc/dqs 13 dm cs dqs dqs dq36 dq37 dq38 dq39 i/o 0 i/o 1 i/o 2 i/o 3 d13 dqs6 dqs 6 dm cs dqs dqs dq48 dq49 dq50 dq51 i/o 0 i/o 1 i/o 2 i/o 3 d6 dm6/dqs15 nc/dqs 15 dm cs dqs dqs dq52 dq53 dq54 dq55 i/o 0 i/o 1 i/o 2 i/o 3 d15 dqs8 dqs 8 dm cs dqs dqs cb0 cb1 cb2 cb3 i/o 0 i/o 1 i/o 2 i/o 3 d8 dm8/dqs17 nc/dqs 17 dm cs dqs dqs cb4 cb5 cb6 cb7 i/o 0 i/o 1 i/o 2 i/o 3 d17 dqs7 dqs 7 dm cs dqs dqs dq56 dq57 dq58 dq59 i/o 0 i/o 1 i/o 2 i/o 3 d7 dm7dqs16 nc/dqs 16 dm cs dqs dqs dq60 dq61 dq62 dq63 i/o 0 i/o 1 i/o 2 i/o 3 d16 dm/ cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d18 dm/ cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d19 dm/ cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d20 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d21 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d23 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d22 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d24 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d26 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d25 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d27 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d28 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d29 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d30 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d32 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d31 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d33 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d35 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 d34 rs 1 * s 0 connects to dcs and s 1 connects to csr on a pair of registers, s 1 connects to dcs and s 0 connects to csr on another pair of registers. ** reset , pck7 and pck 7 connects to all registers. other signals connect to one pair of four registers. signals for address and command parity function par_in ppo qerr register a par_in 100k ohms the resistors on par_in, a14, a15, and the signal line of err_out refer to the section: "register options for unused address inputs" ppo qerr err_out register b par_in - 11 - datasheet ddr2 sdram rev. 1.0 registered dimm 8. absolute maximum dc ratings note : 1. stresses greater than those listed under ?absolute maximum ra tings? may cause permanent damage to the device. this is a stre ss rating only and functional operation of the device at these or any other conditions a bove those indicated in the operational sectio ns of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. storage temperature is the case surface temperature on the ce nter/top side of the dram. for the measurement conditions, plea se refer to jesd51-2 standard. 9. ac & dc operating conditions 9.1 recommended dc operating conditions (sstl - 1.8) note : there is no specific device v dd supply voltage requirement for sstl-1.8 compliance. however under all conditions v ddq must be less than or equal to v dd . 1. the value of v ref may be selected by the user to provide optimum noise margin in the system. typically the value of v ref is expected to be about 0.5 x v ddq of the transmitting device and v ref is expected to track variations in v ddq . 2. peak to peak ac noise on v ref may not exceed +/-2% v ref (dc). 3. v tt of transmitting device must track v ref of receiving device. 4. ac parameters are measured with v dd , v ddq and v ddl tied together. symbol parameter rating units note v dd voltage on v dd pin relative to v ss - 1.0 v ~ 2.3 v v 1 v ddq voltage on v ddq pin relative to v ss - 0.5 v ~ 2.3 v v 1 v ddl voltage on v ddl pin relative to v ss - 0.5 v ~ 2.3 v v 1 v in, v out voltage on any pin relative to v ss - 0.5 v ~ 2.3 v v 1 t stg storage temperature -55 to +100 q c 1, 2 symbol parameter rating units note min. typ. max. v dd supply voltage 1.7 1.8 1.9 v v ddl supply voltage for dll 1.7 1.8 1.9 v 4 v ddq supply voltage for output 1.7 1.8 1.9 v 4 v ref input reference voltage 0.49*v ddq 0.50*v ddq 0.51*v ddq mv 1,2 v tt termination voltage v ref -0.04 v ref v ref +0.04 v 3 - 12 - datasheet ddr2 sdram rev. 1.0 registered dimm 9.2 operating temperature condition note : 1. operating temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions, pl ea se refer to jesd51.2 standard. 2. at 85 - 95 note : 1. input waveform timing is referenced to the input signal crossing through the v ih/il (ac) level applied to the device under test. figure 1. ac input test signal waveform 2. the input signal minimum slew rate is to be maintained over the range from v ref to v ih (ac) min for rising edges and the range from v ref to v il (ac) max for falling edges as shown in the below figure. 3. ac timings are referenced with input waveforms switching from v il (ac) to v ih (ac) on the positive transitions and v ih (ac) to v il (ac) on the negative transitions. symbol parameter rating units note t oper operating temperature 0 to 95 symbol parameter min. max. units note v ih (dc) dc input logic high v ref + 0.125 v ddq + 0.3 v v il (dc) dc input logic low - 0.3 v ref - 0.125 v symbol parameter ddr2-667, ddr2-800 units min. max. v ih (ac) ac input logic high v ref + 0.200 - v v il (ac) ac input logic low - v ref - 0.200 v symbol condition value units note v ref input reference voltage 0.5 * v ddq v1 v swing(max) input signal maximum peak to peak swing 1.0 v 1 slew input signal minimum slew rate 1.0 v/ns 2, 3 v ddq v ih (ac) min v ih (dc) min v ref v il (dc) max v il (ac) max v ss v swing(max) delta tr delta tf v ref - v il (ac) max delta tf falling slew = rising slew = v ih (ac) min - v ref delta tr - 13 - datasheet ddr2 sdram rev. 1.0 registered dimm 10. idd specification parameters definition (idd values are for full operating range of voltage and temperature) symbol proposed conditions units note idd0 operating one bank active-precharge current ; tck = tck(idd), trc = trc(idd), tras = trasmin(idd); cke is high, cs is high between valid commands; address bus inputs are switching; data bus inputs are switching ma idd1 operating one bank active-read-precharge current ; iout = 0ma; bl = 4, cl = cl(idd), al = 0; tck = tck(idd), trc = trc (idd), tras = trasmin(idd), trcd = trcd(idd); cke is high, cs is high between valid commands; address bus inputs are switching; data pattern is same as idd4w ma idd2p precharge power-down current ; all banks idle; tck = tck(idd); cke is low; other cont rol and address bus inputs are stable; data bus inputs are floating ma idd2q precharge quiet standby current ; all banks idle; tck = tck(idd); cke is high, cs is high; other control and address bus inputs are stable; data bus inputs are floating ma idd2n precharge standby current ; all banks idle; tck = tck(idd); cke is high, cs is high; other control and address bus inputs are switching; data bus inputs are switching ma idd3p active power-down current ; all banks open; tck = tck(idd); cke is low; other control and address bus inputs are stable; data bus inputs are floating fast pdn exit mrs(12) = 0 ma slow pdn exit mrs(12) = 1 ma idd3n active standby current ; all banks open; tck = tck(idd), tras = trasmax(idd), trp = trp(idd); cke is high, cs is high between valid commands; other control and address bus inputs ar e switching; data bus inputs are switching ma idd4w operating burst write current ; all banks open, continuous burst writes; bl = 4, cl = cl (idd), al = 0; tck = tck(idd), tras = trasmax(idd), trp = trp(idd); cke is high, cs is high between valid commands; addr ess bus inputs are switching; data bus inputs are switching ma idd4r operating burst read current ; all banks open, continuous burst reads, iout = 0ma; bl = 4, cl = cl(idd), al = 0; tck = tck(idd), tras = tras- max(idd), trp = trp(idd); cke is high, cs is high between valid commands; address bus inputs are switch- ing; data pattern is same as idd4w ma idd5b burst auto refresh current ; tck = tck(idd); refresh command at every trfc(idd) interval; cke is high, cs is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching ma idd6 self refresh current ; ck and ck at 0v; cke d 0.2v; other control and address bus inputs are floating; data bus inputs are floating normal ma low power ma idd7 operating bank interleave read current ; all bank interleaving reads, iout = 0ma; bl = 4, cl = cl (idd), al = trcd(idd)-1*tck(idd); tck = tck(idd), trc = trc(idd), trrd = trrd(idd), tfaw = tfaw(idd), trcd = 1*tck(idd); cke is high, cs is high between valid com- mands; address bus inputs are stable during deselects; data pattern is same as idd4r; refer to the following page for detailed timing conditions ma - 14 - datasheet ddr2 sdram rev. 1.0 registered dimm 11. operating current table : 11.1 m393t2863fba : 1gb(128mx8 *9) module (t a =0 o c, v dd = 1.9v) note : 1. module idd was calculated on the basis of component idd an d can be differently measured according to dq loading cap. 11.2 m393t2863fba : 1gb(128mx8 *9) module - considering register and pll current value (t a =0 o c, v dd = 1.9v) note : 1. idd6 = dram current + standby current of pll and register 2. module idd was calculated on the basis of component idd an d can be differently measured according to dq loading cap. symbol 800@cl=5 800@cl6 667@cl=5 units note ce7 cf7 ce6 idd0 405 405 387 ma idd1 459 459 432 ma idd2p 90 90 90 ma idd2q 180 180 180 ma idd2n 225 225 216 ma idd3p-f 207 207 198 ma idd3p-s 180 180 180 ma idd3n 333 333 315 ma idd4w 648 648 585 ma idd4r 720 720 630 ma idd5b 945 945 900 ma idd6 1 90 90 90 ma idd7 1,440 1,440 1,305 ma symbol 800@cl=5 800@cl=6 667@cl=5 units note ce7 cf7 ce6 idd0 795 995 887 ma idd1 899 1,099 982 ma idd2p 550 570 530 ma idd2q 620 710 640 ma idd2n 585 705 636 ma idd3p-f 637 757 668 ma idd3p-s 610 730 650 ma idd3n 683 873 785 ma idd4w 1,028 1,168 1,035 ma idd4r 1,180 1,310 1,140 ma idd5b 1,325 1615 1,450 ma idd6 1 90 90 90 ma idd7 1,990 2,130 1,885 ma - 15 - datasheet ddr2 sdram rev. 1.0 registered dimm 11.3 m393t5663fba : 2gb(128mx8 *18) module (t a =0 o c, v dd = 1.9v) note : 1. module idd was calculated on the basis of component idd an d can be differently measured according to dq loading cap. 11.4 m393t5663fba : 2gb(128mx8 *18) module - considering register and pll current value (t a =0 o c, v dd = 1.9v) note : 1. idd6 = dram current + standby current of pll and register 2. module idd was calculated on the basis of component idd an d can be differently measured according to dq loading cap. symbol 800@cl=5 800@cl6 667@cl=5 units note ce7 cf7 ce6 idd0 630 630 603 ma idd1 684 684 648 ma idd2p 180 180 180 ma idd2q 360 360 360 ma idd2n 450 450 432 ma idd3p-f 414 414 396 ma idd3p-s 360 360 360 ma idd3n 558 558 531 ma idd4w 873 873 801 ma idd4r 945 945 846 ma idd5b 1,170 1,170 1,116 ma idd6 1 180 180 180 ma idd7 1,665 1,665 1,521 ma symbol 800@cl=5 800@cl=6 667@cl=5 units note ce7 cf7 ce6 idd0 1,320 1,320 1,193 ma idd1 1,454 1,454 1,308 ma idd2p 820 820 760 ma idd2q 1,070 1,070 980 ma idd2n 1,020 1,020 932 ma idd3p-f 1,144 1,144 1,026 ma idd3p-s 1,090 1,090 990 ma idd3n 1,118 1,118 1,021 ma idd4w 1,523 1,523 1,361 ma idd4r 1,735 1,735 1,526 ma idd5b 2,000 2,000 1,796 ma idd6 1 180 180 180 ma idd7 2,695 2,695 2,391 ma - 16 - datasheet ddr2 sdram rev. 1.0 registered dimm 11.5 m393t5660fba : 2gb(256mx4 *18) module (t a =0 o c, v dd = 1.9v) note : 1. module idd was calculated on the basis of component idd an d can be differently measured according to dq loading cap. 11.6 m393t5660fba : 2gb(256mx4 *18) module - considering register and pll current value (t a =0 o c, v dd = 1.9v) note : 1. idd6 = dram current + standby current of pll and register 2. module idd was calculated on the basis of component idd an d can be differently measured according to dq loading cap. symbol 800@cl=5 800@cl6 667@cl=5 units note ce7 cf7 ce6 idd0 810 810 774 ma idd1 918 918 864 ma idd2p 180 180 180 ma idd2q 360 360 360 ma idd2n 450 450 432 ma idd3p-f 414 414 396 ma idd3p-s 360 360 360 ma idd3n 666 666 630 ma idd4w 1,206 1,206 1,080 ma idd4r 1,368 1,368 1,188 ma idd5b 1,890 1,890 1,800 ma idd6 1 180 180 180 ma idd7 2,808 2,808 2,538 ma symbol 800@cl=5 800@cl=6 667@cl=5 units note ce7 cf7 ce6 idd0 1,500 1,500 1,364 ma idd1 1,688 1,688 1,524 ma idd2p 820 820 760 ma idd2q 1,070 1,070 980 ma idd2n 1,020 1,020 932 ma idd3p-f 1,144 1,144 1,026 ma idd3p-s 1,090 1,090 990 ma idd3n 1,226 1,226 1,120 ma idd4w 1,856 1,856 1,640 ma idd4r 2,158 2,158 1,868 ma idd5b 2,720 2,720 2,480 ma idd6 1 180 180 180 ma idd7 3,838 3,838 3,408 ma - 17 - datasheet ddr2 sdram rev. 1.0 registered dimm 11.7 m393t5160fba : 4gb( 256mx4 *36) module (t a =0 o c, v dd = 1.9v) note : 1. module idd was calculated on the basis of component idd an d can be differently measured according to dq loading cap. 11.8 m393t5160fba : 4gb(256mx4 *36) module - considering register and pll current value (t a =0 o c, v dd = 1.9v) note : 1. idd6 = dram current + standby current of pll and register 2. module idd was calculated on the basis of component idd an d can be differently measured according to dq loading cap. symbol 800@cl=5 800@cl6 667@cl=5 units note ce7 cf7 ce6 idd0 1,260 1,260 1,206 ma idd1 1,368 1,368 1,296 ma idd2p 360 360 360 ma idd2q 720 720 720 ma idd2n 900 900 864 ma idd3p-f 828 828 792 ma idd3p-s 720 720 720 ma idd3n 1,116 1,116 1,062 ma idd4w 1,656 1,656 1,512 ma idd4r 1,818 1,818 1,620 ma idd5b 2,340 2,340 2,232 ma idd6 1 360 360 360 ma idd7 3,258 3,258 2,970 ma symbol 800@cl=5 800@cl=6 667@cl=5 units note ce7 cf7 ce6 idd0 2,280 2,280 2,076 ma idd1 2,528 2,528 2,296 ma idd2p 1,310 1,310 1,220 ma idd2q 1,780 1,780 1,640 ma idd2n 1,700 1,700 1,564 ma idd3p-f 1,918 1,918 1,732 ma idd3p-s 1,810 1,810 1,660 ma idd3n 1,906 1,906 1,752 ma idd4w 2,646 2,646 2,362 ma idd4r 2,908 2,908 2,560 ma idd5b 3,560 3,560 3,232 ma idd6 1 360 360 360 ma idd7 4,968 4,968 4,420 ma - 18 - datasheet ddr2 sdram rev. 1.0 registered dimm 12. input/output capacitance (v dd =1.8v, v ddq =1.8v, ta=25 o c ) note : dm is internally loaded to match dq and dqs identically. 13. electrical characteristics & ac timing for ddr2-800/667 (0 speed ddr2-800(e7) ddr2-800(f7) ddr2-667(e6) units bin (cl - trcd - trp) 5 - 5 - 5 6 - 6- 6 5 - 5 - 5 parameter min max min max min max tck, cl=3 5 8 - - 5 8 ns tck, cl=4 3.75 8 3.75 8 3.75 8 ns tck, cl=5 2.5 8 3 8 3 8 ns tck, cl=6 - - 2.5 8 - - ns trcd 12.5 - 15 - 15 - ns trp 12.5 - 15 - 15 - ns trc 57.5 - 60 - 60 - ns tras 45 70000 45 70000 45 70000 ns parameter sym. min max min max min max min max units part-number m393t2863fba m393t5663fba m393t5660fba m393t5160fba input capacitance, ck and ck cck - 11 - 11 - 11 - 11 pf input capacitance, cke and cs ci1 - 12 - 12 - 12 - 12 input capacitance, address, ras ,cas ,we ci2 - 12 - 12 - 12 - 12 input/output capacitance, dq, dm, dqs, dqs cio - 10 - 10 - 10 - 10 parameter symbol 256mb 512mb 1gb 2gb 4gb units refresh to active/refresh command time trfc 75 105 127.5 195 327.5 ns average periodic refresh interval trefi 0 ? < ? - 19 - datasheet ddr2 sdram rev. 1.0 registered dimm 13.3 timing parameters by speed grade (refer to notes for informations related to this table at the component datasheet) parameter symbol ddr2-800 ddr2-667 units note min max min max dq output access time from ck/ck tac -400 400 - 450 450 ps 40 dqs output access time from ck/ck tdqsck -350 350 - 400 400 ps 40 average clock high pulse width tch(avg) 0.48 0.52 0.48 0.52 tck(avg) 35,36 average clock low pulse width tcl(avg) 0.48 0.52 0.48 0.52 tck(avg) 35,36 ck half pulse period thp min(tcl(abs), tch(abs)) x min(tcl(abs), tch(abs)) x ps 37 average clock period tck(avg) 2500 8000 3000 8000 ps 35,36 dq and dm input hold time tdh(base) 125 x 175 x ps 6,7,8,21,28,31 dq and dm input setup time tds(base) 50 x 100 x ps 6,7,8,20,28,31 control & address input pulse width for each input tipw 0.6 x 0.6 x tck(avg) dq and dm input pulse width for each input tdipw 0.35 x 0.35 x tck(avg) data-out high-impedance time from ck/ck thz x tac(max) x tac(max) ps 18,40 dqs/dqs low-impedance time from ck/ck tlz(dqs) tac(min) tac(max) tac(min) tac(max) ps 18,40 dq low-impedance time from ck/ck tlz(dq) 2* tac(min) tac(max) 2* tac(min) tac(max) ps 18,40 dqs-dq skew for dqs and associated dq signals tdqsq x 200 x 240 ps 13 dq hold skew factor tqhs x 300 x 340 ps 38 dq/dqs output hold time from dqs tqh thp - tqhs x thp - tqhs x ps 39 dqs latching rising transitions to associated clock edges tdqss - 0.25 0.25 -0.25 0.25 tck(avg) 30 dqs input high pulse width tdqsh 0.35 x 0.35 x tck(avg) dqs input low pulse width tdqsl 0.35 x 0.35 x tck(avg) dqs falling edge to ck setup time tdss 0.2 x 0.2 x tck(avg) 30 dqs falling edge hold time from ck tdsh 0.2 x 0.2 x tck(avg) 30 mode register set command cycle time tmrd 2 x 2 x nck mrs command to odt update delay tmod 0 12 0 12 ns 32 write postamble twpst 0.4 0.6 0.4 0.6 tck(avg) 10 write preamble twpre 0.35 x 0.35 x tck(avg) address and control input hold time tih(base) 250 x 275 x ps 5,7,9,23,29 address and control input setup time tis(base) 175 x 200 x ps 5,7,9,22,29 read preamble trpre 0.9 1.1 0.9 1.1 tck(avg) 19,41 read postamble trpst 0.4 0.6 0.4 0.6 tck(avg) 19,42 activate to activate command period for 1kb page size products trrd 7.5 x 7.5 x ns 4,32 activate to activate command period for 2kb page size products trrd 10 x 10 x ns 4,32 - 20 - datasheet ddr2 sdram rev. 1.0 registered dimm parameter symbol ddr2-800 ddr2-667 units note min max min max four activate window for 1kb page size products tfaw 35 x 37.5 x ns 32 four activate window for 2kb page size products tfaw 45 x 50 x ns 32 cas to cas command delay tccd 2 x 2 x nck write recovery time twr 15 x 15 x ns 32 auto precharge write recovery + precharge time tdal wr + tnrp x wr + tnrp x nck 33 internal write to read command delay twtr 7.5 x7.5 x ns 24,32 internal read to precharge command delay trtp 7.5 x 7.5 x ns 3,32 exit self refresh to a non-read command txsnr trfc + 10 xtrfc + 10 x ns 32 exit self refresh to a read command txsrd 200 x200 x nck exit precharge power down to any command txp 2 x 2 x nck exit active power down to read command txard 2 x 2 x nck 1 exit active power down to read command (slow exit, lower power) txards 8 - al x 7 - al x nck 1,2 cke minimum pulse width (high and low pulse width) tcke 3 x 3 x nck 27 odt turn-on delay taond 2 2 2 2 nck 16 odt turn-on taon tac(min) tac(max)+0.7 tac(min) tac(max)+0.7 ns 6,16,40 odt turn-on (power-down mode) taonpd tac(min)+2 2*tck(avg) +tac(max)+1 tac(min)+2 2*tck(avg) +tac(max)+1 ns odt turn-off delay taofd 2.5 2.5 2.5 2.5 nck 17,45 odt turn-off taof tac(min) tac(max)+0.6 tac(min) tac(max)+0.6 ns 17,43,45 odt turn-off (power-down mode) taofpd tac(min)+2 2.5*tck(avg)+ tac(max)+1 tac(min)+2 2.5*tck(avg)+ tac(max)+1 ns odt to power down entry latency tanpd 3 x3 x nck odt power down exit latency taxpd 8 x8 x nck ocd drive mode output delay toit 0 12 0 12 ns 32 minimum time clocks remains on after cke asynchronously drops low tdelay tis+tck(avg) +tih x tis+tck(avg) +tih xns15 - 21 - datasheet ddr2 sdram rev. 1.0 registered dimm 14. physical dimensions : 14.1 128mbx8 based 128mx72 module (1 rank) - m393t2863fba units : millimeters the used device is 128m x8 ddr2 sdram, flip-chip. ddr2 sdram part no : k4t1g084qf 2.50 1.00 0.20 2.500.20 detail b 5.00 detail a 4.00 1.500.10 0.800.05 4.00 3.80 3.00 4.00 1.27 0.10 2.70 max 1.0 max 30.00 a b 63.00 55.00 register pll - 22 - datasheet ddr2 sdram rev. 1.0 registered dimm 14.2 128mbx8/256mbx4 based 256mx72 module (2 ranks / 1 rank) - m393t5663fba/m393t5660fba units : millimeters the used device is 128m x8 / 256m x4 ddr2 sdram, flip-chip. ddr2 sdram part no : k4t1g084qf / k4t1g044qf 1.27 0.10 4.00 max 1.0 max 2.50 1.00 0.20 2.500.20 detail b 5.00 detail a 4.00 1.500.10 0.800.05 4.00 3.80 3.00 4.00 133.35 30.00 a b 63.00 55.00 register pll register - 23 - datasheet ddr2 sdram rev. 1.0 registered dimm 14.3 256mbx4 based 512mx72 module (2 ranks) - m393t5160fba units : millimeters the used device is 256m x4 ddr2 sdram, flip-chip. ddr2 sdram part no : k4t1g044qf 2.50 1.00 0.20 2.500.20 detail b 5.00 detail a 4.00 1.500.10 0.800.05 4.00 3.80 3.00 4.00 1.27 0.10 4.00 max 1.0 max 133.35 30.00 a b 63.00 55.00 pll register register - 24 - datasheet ddr2 sdram rev. 1.0 registered dimm 15. 240 pin ddr2 registered dimm clock topology ck0 ck 0 pll out1 outn reg.a reg.b feedback in feedback out in 0ns (nominal) c 120 ohms 120 ohms 120 ohms 120 ohms c note : 1. the clock delay from the input of the pll clock to the input of any ddr2 sdram or register will be set to 0ns (nominal). 2. input, output, and feedback clock lines are terminated fr om line to line as shown, and not from line to ground. 3. only one pll output is shown per output type. any additional pll outputs will be wired in a similar manner. 4. termination resistors for the pll feedback path clocks are lo cated as close to the input pin of the pll as possible. ddr2 sdram ddr2 sdram |
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